In many semiconductor devices such as embedded processors, systems-on-a-chip (SOC), or other computer systems or consumer electronic devices, on-chip busses are becoming faster and wider with many associated register queues and related logic in attached unit interfaces. Split transaction capabilities on these busses have added significant depth to these queues. This is leading to a situation where on-chip busses and their associated interfaces will become a significant portion of overall system power, particularly in SOC designs.
Previous efforts to reduce power consumption on busses and their associated attached units have included powering down individual units when they are not in use and reducing bus frequencies. In embedded processors and SOC designs, there may be large variances in work loads depending on the applications currently executing, time of day, type of traffic, etc. The variations in workload are often under the control of various independent software drivers. These drivers typically control their particular units but do not control system resources such as busses.
In prior systems, in order to control system resources such as busses, additional communication with software that manages system resources is typically used. The overhead and latency involved with using software to power manage system resources such as busses can be significant. This latency reduces the value of power managing system resources such as busses that need to be able to quickly change speeds based on current workload.